The design and fabrication of high-performance signaling mechanisms for digital integrated circuit devices has become a significant challenge. For example, with respect to high-performance memory integrated circuit devices, ensuring the reliability in the design and fabrication of the signaling components of such devices (e.g., high performance DDR memory) has become problematic. In the past, slower memory bus speeds allowed significant specification margins in the design and fabrication of a given memory module. However, modern memory integrated circuit designs require exacting control of critical timing specifications, and design parameters must be strictly maintained to keep the entire system in balance. A variable signal delay element is a mechanism used to compensate for timing irregularities and calibrate sensitive signaling components. What is needed is an effective controllable delay chain that provides for minimal power expenditure, high reliability, speed, and proper timing to insure an overall system (e.g., CPU, bridge components, peripheral busses, etc.) operates at peak performance.